Current-sensing Completion Detection Methodology and Its Implementation in Asynchronous Systems

This paper addresses an alternative approach to detecting the completion of computation in asynchronous digital circuits. Presented method, as the name suggests, is based on sensing the amount of current drawn by the combinatorial logic and exploits the behavior of CMOS logic gates for separating the computation state from the idle state. The paper deals with the current sensor design, its implementation into the various asynchronous pipeline systems, and discusses the advantages over the conventional approaches.